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| (R) ISD2500 Series Single-Chip Voice Record/Playback Devices 32-*, 40-*, 48-*, 64-*, 60-, 75-, 90-, and 120-Second Durations FEATURES * * * Easy-to-use single-chip voice Record/ Playback solution High-quality, natural voice/audio reproduction Manual switch or microcontroller compatible Playback can be edge- or levelactivated Single-chip durations of 32*, 40*, 48*, 64*, 60, 75, 90, and 120 seconds Directly cascadable for longer durations Automatic Power-Down (Push-Button Mode) - Standby current 1 A (typical) Zero-power message storage - Eliminates battery backup circuits * * * * * * * * Fully addressable to handle multiple messages 100-year message retention (typical) 100,000 record cycles (typical) On-chip clock source No algorithm development required Single +5 volt power supply Available in die form, DIP, SOIC, and TSOP packaging Industrial temperature (-40C to +85C) versions available 1 * * * * ISD2500 SERIES SUMMARY Part Number ISD2560 ISD2575 ISD2590 ISD25120 Duration (Seconds) 60 75 90 120 Input Sample Rate (KHz) 8.0 6.4 5.3 4.0 Typical Filter Pass Band (KHz) 3.4 2.7 2.3 1.7 ISD2532* ISD2540* ISD2548* ISD2564* 32 40 48 64 8.0 6.4 5.3 4.0 3.4 2.7 2.3 1.7 Information Storage Devices, Inc. * Advance information: ISD2532/40/48/64 devices. 1-79 ISD2500 Series Product Data Sheets GENERAL DESCRIPTION Information Storage Devices' ISD2500 ChipCorder(R) Series provides high-quality, single-chip Record/Playback solutions for 32- to 120-second messaging applications. The CMOS devices include an on-chip oscillator, microphone preamplifier, automatic gain control, antialiasing filter, smoothing filter, speaker amplifier, and high density multi-level storage array. In addition, the ISD2500 is microcontroller compatible, allowing complex messaging and addressing to be achieved. Recordings are stored in on-chip nonvolatile memory cells, providing zero-power message storage. This unique, single-chip solution is made possible through ISD's patented multilevel storage technology. Voice and audio signals are stored directly into memory in their natural form, providing highquality, solid-state voice reproduction. DETAILED DESCRIPTION Speech/Sound Quality The ISD2500 Series includes devices offered at 4.0, 5.3, 6.4, and 8.0 KHz sampling frequencies, allowing the user a choice of speech quality options. Increasing the duration within a product series decreases the sampling frequency and bandwidth, which affects sound quality. Please refer to the ISD2500 Series Summary table on page 1-79 to compare filter pass band and product durations. The speech samples are stored directly into onchip nonvolatile memory without the digitization and compression associated with other solutions. Direct analog storage provides a very true, natural sounding reproduction of voice, music, tones, and sound effects not available with most solid-state digital solutions. -1 Duration To meet end system requirements, the ISD2500 Series offers single-chip solutions at 32*, 40*, 48*, 64*, 60, 75, 90, and 120 seconds. Parts may also be cascaded together for longer durations. ISD2560/75/90/120 DEVICE BLOCK DIAGRAM Internal Clock XCLK 5-Pole Active Antialiasing Filter Timing Sampling Clock R ANA IN ANA OUT MIC MIC REF AGC PreAmp Amp Analog Transceivers Decoders 480 K Cell Nonvolatile Multilevel Storage Array 5-Pole Active Smoothing Filter SP+ Mux Amp SP- Automatic Gain Control (AGC) Power Conditioning Address Buffers Device Control VCCA VSSA VSSD VCCD A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 PD OVF P/R CE EOM AUX IN 1-80 * Advance information: ISD2532/40/48/64 devices. Product Data Sheets ISD2500 Series ISD2532/40/48/64* DEVICE BLOCK DIAGRAM Internal Clock XCLK 5-Pole Active Antialiasing Filter Decoders Timing Sampling Clock Amp Analog Transceivers 256 K Cell Nonvolatile Multilevel Storage Array R ANA IN ANA OUT MIC MIC REF AGC PreAmp 5-Pole Active Smoothing Filter SP+ Mux Amp SP- Automatic Gain Control (AGC) Power Conditioning Address Buffers Device Control VCCA VSSA VSSD VCCD A0 A1 A2 A3 A4 A5 A6 A7 A8 PD OVF P/R CE EOM AUX IN EEPROM Storage One of the benefits of ISD's ChipCorder technology is the use of on-chip nonvolatile memory, providing zero-power message storage. The message is retained for up to 100 years typically without power. In addition, the device can be rerecorded typically over 100,000 times. PIN DESCRIPTIONS Voltage Inputs (VCCA, VCCD) To minimize noise, the analog and digital circuits in the ISD2500 Series devices use separate power busses. These voltage busses are brought out to separate pins and should be tied together as close to the supply as possible. In addition, these supplies should be decoupled as close to the package as possible. 1 Microcontroller Interface In addition to its simplicity and ease of use, the ISD2500 Series includes all the interfaces necessary for microcontroller-driven applications. The address and control lines can be interfaced to a microcontroller and manipulated to perform a variety of tasks, including message assembly, message concatenation, predefined fixed message segmentation, and message management. Ground Inputs (VSSA, VSSD) The ISD2500 Series of devices utilizes separate analog and digital ground busses. These pins should be connected separately through a lowimpedance path to power supply ground. Power Down Input (PD) Programming The ISD2500 Series is also ideal for playback-only applications, where single or multiple messages are referenced through buttons, switches, or a microcontroller. Once the desired message configuration is created, duplicates can easily be generated via an ISD programmer. When not recording or playing back, the PD pin should be pulled HIGH to place the part in a very low power mode (see ISB specification). When OVF pulses LOW for an overflow condition, PD should be brought HIGH to reset the address pointer back to the beginning of the Record/Playback space. The PD pin has additional functionality in the M6 (Push-Button) Operational * Advance information: ISD2532/40/48/64 devices. 1-81 ISD2500 Series Product Data Sheets ISD2560/75/90/120 DEVICE PINOUTS OVF CE PD EOM XCLK P/R VCCD NC NC A0/M0 A1/M1 A2/M2 A3/M3 A4/M4 A5/M5 A6/M6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ISD2560/75/90/120 ANA OUT ANA IN AGC MIC REF MIC VCCA SP- NC NC SP+ VSSA VSSD AUX IN A9 A8 A7 A0/M0 A1/M1 A2/M2 A3/M3 A4/M4 A5/M5 A6/M6 A7 A8 A9 AUX IN VSSD VSSA SP+ 1 2 3 4 5 6 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ISD2560 7 ISD2575 8 ISD2590 9 ISD25120 10 11 12 13 14 VCCD P/R XCLK EOM PD CE OVF ANA OUT ANA IN AGC MIC REF MIC VCCA SP- TSOP DIP/SOIC Mode described later in the Operational Mode section. End-Of-Message / RUN Output (EOM) A nonvolatile marker is automatically inserted at the end of each recorded message. It remains there until the message is recorded over. The EOM output pulses LOW for a period of TEOM at the end of each message. In addition, the ISD2500 Series has an internal VCC detect circuit to maintain message integrity should VCC fall below 3.5V. In this case, EOM goes LOW and the device is fixed in Playback-only mode. When the device is configured in Operational Mode M6 (Push-Button Mode), this pin provides an active-HIGH RUN signal, indicating the device is currently recording or playing. This signal can conveniently drive an LED for a visual indicator of a Record or Playback operation in process. -1 Chip Enable Input (CE) The CE pin is taken LOW to enable all Playback and Record operations. The address inputs and Playback/Record input (P/R) are latched by the falling edge of CE. CE has additional functionality in the M6 (Push-Button) Operational Mode described later in the Operational Mode section. Playback/Record Input (P/R) The P/R input is latched by the falling edge of the CE pin. A HIGH level selects a Playback cycle while a LOW level selects a Record cycle. For a Record cycle, the address inputs provide the starting address and recording continues until PD or CE is pulled HIGH or an overflow is detected (i.e. the chip is full). When a Record cycle is terminated by pulling PD or CE HIGH, an End-Of-Message (EOM) marker is stored at the current address in memory. For a Playback cycle, the address inputs provide the starting address and the device will play until an EOM marker is encountered. The device can continue past an EOM marker in an operational mode, or if CE is held LOW in address mode. (See page 1-85 for more Operational Modes). Overflow Output (OVF) This signal pulses LOW at the end of memory space, indicating the device has been filled and the message has overflowed. The OVF output then follows the CE input until a PD pulse has reset the device. This pin can be used to cascade several ISD2500 devices together to increase Record/ Playback durations. 1-82 * Advance information: ISD2532/40/48/64 devices. Product Data Sheets ISD2500 Series ISD2532/40/48/64* DEVICE PINOUTS OVF CE PD EOM XCLK P/R VCCD NC NC A0/M0 A1/M1 A2/M2 A3/M3 A4/M4 A5/M5 A6/M6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ISD2532/40/48/64 ANA OUT ANA IN AGC MIC REF MIC VCCA SP- NC NC SP+ VSSA VSSD AUX IN A8 A7 NC A0/M0 A1/M1 A2/M2 A3/M3 A4/M4 A5/M5 A6/M6 NC A7 A8 AUX IN VSSD VSSA SP+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ISD2532 ISD2540 ISD2548 ISD2564 VCCD P/R XCLK EOM PD CE OVF ANA OUT ANA IN AGC MIC REF MIC VCCA SP- TSOP DIP/SOIC Microphone Input (MIC) The microphone input transfers its signal to the onchip preamplifier. An on-chip Automatic Gain Control (AGC) circuit controls the gain of this preamplifier from -15 to 24 dB. An external microphone should be AC coupled to this pin via a series capacitor. The capacitor value, together with the internal 10 K ohm resistance on this pin, determines the low-frequency cutoff for the ISD2500 Series passband. See ISD's Application Notes and Design Manual in this book for additional information on low-frequency cutoff calculation. AGC pin to VSSA analog ground. The "release" time is determined by the time constant of an external resistor (R2) and an external capacitor (C2) connected in parallel between the AGC Pin and VSSA analog ground. Nominal values of 470 K and 4.7 F give satisfactory results in most cases. 1 Analog Output (ANA OUT) This pin provides the preamplifier output to the user. The voltage gain of the preamplifier is determined by the voltage level at the AGC pin. Microphone Reference Input (MIC REF) The MIC REF input is the inverting input to the microphone preamplifier. This provides a noisecanceling or common-mode rejection input to the device when connected to a differential microphone. Analog Input (ANA IN) The analog input pin transfers its signal to the chip for recording. For microphone inputs, the ANA OUT pin should be connected via an external capacitor to the ANA IN pin. This capacitor value, together with the 3.0 K input impedance of ANA IN, is selected to give additional cutoff at the lowfrequency end of the voice passband. If the desired input is derived from a source other than a microphone, the signal can be fed, capacitively coupled, into the ANA IN pin directly. Automatic Gain Control Input (AGC) The AGC dynamically adjusts the gain of the preamplifier to compensate for the wide range of microphone input levels. The AGC allows the full range of whispers to loud sounds to be recorded with minimal distortion. The "attack" time is determined by the time constant of a 5 K internal resistance and an external capacitor (C2 on the schematic on page 1-100) connected from the External Clock Input (XCLK) The external clock input for the ISD2500 devices has an internal pull-down device. These devices are configured at the factory with an internal sampling clock frequency centered to 1% of * Advance information: ISD2532/40/48/64 devices. 1-83 ISD2500 Series specification. The frequency is then maintained to a variation of 2.25% over the entire commercial temperature and operating voltage ranges. The internal clock has a 5% tolerance over the industrial temperature and voltage range. A regulated power supply is recommended for industrial temperature range parts. If greater precision is required, the device can be clocked through the XCLK pin as follows: NOTE Product Data Sheets Connection of speaker outputs in parallel may cause damage to the device. A single output may be used alone (including a coupling capacitor between the SP pin and the speaker). These outputs may be used individually with the output signal taken from either pin. Using the differential outputs results in a 4:1 improvement in output power. NOTE Part Number ISD2560 ISD2575 ISD2590 Sample Rate 8.0 KHz 6.4 KHz 5.3 KHz 4.0 KHz Required Clock 1024 KHz 819.2 KHz 682.7 KHz 512 KHz Never ground or drive an unused speaker output. Auxiliary Input (AUX IN) The Auxiliary Input is multiplexed through to the output amplifier and speaker output pins when CE is HIGH, P/R is HIGH, and Playback is currently not active or if the device is in Playback overflow. When cascading multiple ISD2500 devices, the AUX IN pin is used to connect a Playback signal from a following device to the previous output speaker drivers. For noise considerations, it is suggested that the auxiliary input not be driven when the storage array is active. -1 ISD25120 ISD2532* ISD2540* ISD2548* ISD2564* 8.0 KHz 6.4 KHz 5.3 KHz 4.0 KHz 1024 KHz 819.2 KHz 682.7 KHz 512 KHz These recommended clock rates should not be varied because the antialiasing and smoothing filters are fixed, and aliasing problems can occur if the sample rate differs from the one recommended. The duty cycle on the input clock is not critical, as the clock is immediately divided by two. IF THE XCLK IS NOT USED, THIS INPUT MUST BE CONNECTED TO GROUND. Address/Mode Inputs (Ax/Mx) The Address/Mode Inputs have two functions depending on the level of the two Most Significant Bits (MSB) of the address (A8 and A9 for the ISD256075/90/120 devices, and A7 and A8 for the ISD2532/40/48/64* devices). If either or both of the two MSBs are LOW, the inputs are ALL interpreted as address bits and are used as the start address for the current Record or Playback cycle. The address pins are inputs only and do not output internal address information as the operation progresses. Address inputs are latched by the falling edge of CE. If both MSBs are HIGH, the Address/Mode Inputs are interpreted as Mode bits according to the Operational Mode table on page 1-85. There are six operational modes (M0..M6) available as indi- Speaker Outputs (SP+/SP-) All devices in the ISD2500 Series include an onchip differential speaker driver, capable of driving 50 milliwatts into 16 from AUX IN (12.2 mW from memory). The speaker outputs are held at VSSA levels during record and power down. It is therefore not possible to parallel speaker outputs of multiple ISD2500 devices or the outputs of other speaker drivers. 1-84 * Advance information: ISD2532/40/48/64 devices. Product Data Sheets ISD2500 Series OPERATIONAL MODES TABLE Mode Control M0 M1 M2 M3 M4 M5 M6 Function Message cueing Delete EOM markers Not applicable Looping Consecutive addressing CE level-activated Push-button control Typical Use Fast-forward through messages Position EOM marker at the end of the last message Reserved Continuous playback from Address 0 Record/Play multiple consecutive messages Allows message pausing Simplified device interface Jointly Compatible* M4, M5, M6 M3, M4, M5, M6 N/A M1, M5, M6 M0, M1, M5 M0, M1, M3, M4 M0, M1, M3 NOTE: An asterisk (*) indicates additional operational modes which can be used simultaneously with the given mode. 1 cated in the table. It is possible to use multiple operational modes simultaneously. Operational Modes are sampled on each falling edge of CE, and thus Operational Modes and direct addressing are mutually exclusive. OPERATIONAL MODES The ISD2500 Series is designed with several builtin operational modes that provide maximum functionality with minimum additional components. These are described in detail below. The operational modes use the address pins on the ISD2500 devices, but are mapped outside the valid address range. When the two Most Significant Bits (MSBs) are HIGH (A8 and A9 for the ISD2560/75/90/120 devices, and A7 and A8 for the ISD2532/40/48/64* devices), the remaining address signals are interpreted as mode bits and not as address bits. Therefore, operational modes and direct addressing are not compatible and cannot be used simultaneously. There are two important considerations for using operational modes. First, all operations begin initially at address 0, which is the beginning of the ISD2500 address space. Later operations can begin at other address locations, depending on the operational mode(s) chosen. In addition, the address pointer is reset to 0 when the device is changed from Record to Playback, Playback to Record (except M6 mode), or when a Power-Down cycle is executed. Second, Operational Modes are executed when CE goes LOW and the two MSBs are HIGH. This Operational Mode remains in effect until the next LOW-going CE signal, at which point the current address/mode levels are sampled and executed. OPERATIONAL MODES DESCRIPTION The Operational Modes can be used in conjunction with a microcontroller, or they can be hard-wired to provide the desired system operation. M0 -- Message Cueing Message Cueing allows the user to skip through messages, without knowing the actual physical addresses of each message. Each CE LOW pulse causes the internal address pointer to skip to the next message. This mode should be used for * Advance information: ISD2532/40/48/64 devices. 1-85 ISD2500 Series Product Data Sheets Playback only, and is typically used with the M4 Operational Mode. M6 -- Push-Button Mode The ISD2500 Series of devices contain a PushButton operational mode. The Push-Button mode is used primarily in very low-cost applications and is designed to minimize external circuitry and components, thereby reducing system cost. In order to configure the device in Push-Button operational mode, the two most significant address bits must be HIGH, and the M6 mode pin must also be HIGH. A device in this mode always powers down at the end of each Playback or Record cycle after CE goes HIGH. When this operational mode is implemented, several of the pins on the device have alternate functionality: M1 -- Delete EOM Markers The M1 Operational Mode allows sequentially recorded messages to be combined into a single message with only one EOM marker set at the end of the final message. When this operational mode is configured, messages recorded sequentially are played back as one continuous message. M2 -- Unused When operational modes are selected, the M2 pin should be LOW. M3 -- Message Looping -1 The M3 Operational Mode allows for the automatic, continuously repeated playback of the message located at the beginning of the address space. A message CAN completely fill the ISD2500 device and will loop from beginning to end without OVF going LOW. Pin Name CE PD EOM Alternate Functionality in Push-Button Mode Start/Pause Push-Button (LOW pulse-activated) Stop/Reset Push-Button (HIGH pulse activated) Active-HIGH Run Indicator M4 -- Consecutive Addressing During normal operations, the address pointer will reset when a message is played through to an EOM marker. The M4 Operational Mode inhibits the address pointer reset on EOM, allowing messages to be played back consecutively. CE Pin (START/PAUSE) In Push-Button Operational Mode, CE acts as a LOW-going pulse-activated START/PAUSE signal. If no operation is currently in progress, a LOWgoing pulse on this signal will initiate a Playback or a Record cycle according to the level on the P/R pin. A subsequent pulse on the CE pin, before an End-Of-Message is reached in Playback or an overflow condition occurs, will cause the device to pause. The address counter is not reset, and another CE pulse will cause the device to continue the operation from the place where it was paused. M5 -- CE-Level Activated The default mode for ISD2500 devices is for CE to be edge-activated on Playback and level-activated on Record. The M5 Operational Mode causes the CE pin to be interpreted as level-activated as opposed to edge-activated during Playback. This is specifically useful for terminating Playback operations using the CE signal. In this mode, CE LOW begins a Playback cycle, at the beginning of the device memory. The Playback cycle continues as long as CE is held LOW. When CE goes HIGH, Playback will immediately end. A new CE LOW will restart the message from the beginning unless M4 is also HIGH. PD Pin (STOP/RESET) In push-button Operational Mode, PD acts as a HIGH-going pulse-activated STOP/RESET signal. When a Playback or Record cycle is in progress and a HIGH-going pulse is observed on PD, the 1-86 * Advance information: ISD2532/40/48/64 devices. Product Data Sheets ISD2500 Series current cycle is terminated and the address pointer is reset to address 0, the beginning of the message space. Playback in Push-Button Mode 1. The PD pin should be LOW. 2. The P/R pin is taken HIGH. EOM Pin (RUN) In Push-Button Operational Mode, EOM becomes an active-HIGH RUN signal which can be used to drive an LED or other external device. It is HIGH whenever a Record or Playback operation is in progress. Recording in Push-Button Mode 3. The CE pin is pulsed LOW. Playback starts, EOM goes HIGH to indicate an operation in progress. 4. If the CE pin is pulsed LOW or an EOM marker is encountered during an operation, the part will pause. The internal address pointers are not cleared, and EOM goes back LOW. The P/R pin may be changed at this time. A subsequent Record operation would not reset the address pointers and the recording would begin where Playback ended. 5. CE is again pulsed LOW. Playback starts where it left off, with EOM going HIGH to indicate an operation in progress. 6. Playback continues as in steps 4 and 5 until PD is pulsed HIGH or overflow occurs. 7. If in overflow, pulling CE LOW will reset the address pointer and start Playback from the beginning. After a PD pulse, the part is reset to address 0. NOTE 1. The PD pin should be LOW, usually using a pulldown resistor. 2. The P/R pin is taken LOW. 3. The CE pin is pulsed LOW. Recording starts, EOM goes HIGH to indicate an operation in progress. 4. The CE pin is pulsed LOW. Recording pauses, EOM goes back LOW. The internal address pointers are not cleared, but an EOM marker is stored in memory to point to the message end. The P/R pin may be taken HIGH at this time. Any subsequent CE would start a playback at address 0. 5. The CE pin is pulsed LOW. Recording starts at the next address after the previous set EOM marker. EOM goes back HIGH. NOTE 1 Push-button mode can be used in conjunction with modes M0, M1, and M3. If the M1 operational mode pin is also HIGH, the just previously written EOM bit is erased, and recording starts at that address.) 6. When the recording sequences are finished, the final CE pulse LOW will end the last Record cycle, leaving a set EOM marker at the message end. Recording may also be terminated by a HIGH level on PD, which will leave a set EOM marker. Good Audio Design Practices ISD products are very high-quality single-chip voice Recording and Playback systems. To ensure the highest quality voice reproduction, it is important that good audio design practices on layout and power supply decoupling be followed. See the ISD Application Notes and Design Manual in this book for details. * Advance information: ISD2532/40/48/64 devices. 1-87 ISD2500 Series Product Data Sheets ISD1000A COMPATIBILITY The ISD2500 Series of devices is designed to provide upward compatibility with the ISD1000A family. When designing with the ISD2500 Series, the following differences should be noted. Push-Button Mode The ISD2500 Series includes an additional Operational Mode called Push-Button mode. This provides an alternative interface to the Record and Playback functions of the part. The CE and PD pins become redefined as edge-activated "pushbuttons." A pulse on CE initiates a cycle, and if triggered again, pauses the current cycle without resetting the address pointer (i.e., a Start or Pause function). PD stops any current cycle and resets the address pointer to the beginning of the message space (i.e., a Stop and Reset function). Additionally, the EOM pin functions as an activeHIGH run indicator, and can be used to drive an LED indicating a Record or Playback operation is in progress. Devices in the Push-Button mode cannot be cascaded. Addressing The ISD2560/75/90/120 devices have 480K storage cells designed to provide 60 seconds of storage at a sampling rate of 8.0 KHz. This is approximately four times the storage of the ISD1000A family. To enable the same addressing resolution, two additional address pins have been added. The address space of each device is divisible into 300 increments with valid addressing from 00 to 13F Hex. Some higher addresses are mapped into the Operational Modes. All other addresses are invalid. The ISD2532/40/48/64 devices have 256K storage cells designed to provide 32 seconds of storage at a sampling rate of 8.0 KHz. This is twice the amount of storage of the ISD1000A family. To enable the same addressing resolution, one additional address pin has been added. The address space of each device is divisable into 320 increments with valid addressing from 00 to 13F Hex. -1 Looping Mode The ISD2500 Series can loop with a message that completely fills the memory space. NOTE Additional descriptions of ISD2500 device functionality and application examples are provided in the ISD Application Notes and Design Manual in this book. Overflow The ISD1000A Series combined two functions on the EOM pin: end-of-message indication and overflow. The ISD2500 separates these two functions. Pin 25 (PDIP package) remains as EOM, but outputs only the EOM signal indication. Pin 22 (PDIP package) becomes OVF and pulses LOW only when the device reaches its end of memory, or is "full." This change allows easy message cueing and addressability across device boundaries. This also means that the M2 operational mode found in the ISD1000A family is not implemented in the ISD2500 Series. 1-88 * Advance information: ISD2532/40/48/64 devices. Product Data Sheets ISD2500 Series TIMING DIAGRAMS Record CE TCE TSET P/R THOLD PD Don't Care Don't Care T PDH TPDS TPDR A0-A9 MIC ANA IN OVF Don't Care TSET TPUD Don't Care TOVF 1 Playback CE TSET P/R THOLD PD Don't Care TCE Don't Care T PDH TPDS TPDP A0-A9 Don't Care TSET Don't Care SP+/- TOVF OVF EOM TPUD TEOM * Advance information: ISD2532/40/48/64 devices. 1-89 ISD2500 Series Product Data Sheets ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS) Condition Junction temperature Storage temperature range Voltage applied to any pin Value 150 C -65 C to +150 C (VSS - 0.3 V) to (VCC + 0.3 V) (VSS - 1.0 V) to (VCC + 1.0 V) 300 C OPERATING CONDITIONS (PACKAGED PARTS) Condition Commercial operating temperature range(1) Industrial operating temperature range(1) Supply voltage (VCC)(2) Ground voltage (VSS)(3) NOTES: 1. Case temperature. 2. VCC = VCCA = VCCD. 3. VSS = VSSA = VSSD. Value 0 C to +70 C -40 C to +85 C Voltage applied to any pin (Input current limited to 20 mA) Lead temperature (soldering - 10 seconds) VCC - VSS NOTE: +4.5 V to +5.5 V 0V - 0.3 V to + 7.0 V -1 Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability. Functional operation is not implied at these conditions. DC PARAMETERS (PACKAGED PARTS) Symbol VIL VIH VOL VOH VOH1 VOH2 ICC ISB IIL IILPD REXT RMIC RAUX Parameters Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage OVF Output High Voltage EOM Output High Voltage VCC Current (Operating) VCC Current (Standby) Input Leakage Current Input Current HIGH w/Pull Down Output Load Impedance Preamp In Input Resistance AUX INPUT Resistance 16 4 5 9 11 15 20 VCC-0.4 2.4 VCC-1.0 VCC-0.8 25 1 30 10 +1 130 2.0 0.4 Min(2) Typ (1) Max(2) 0.8 Units V V V V V V mA A A A K K Force VCC (4) Speaker Load MIC and MIC REF Pins IOL = 4.0 mA IOH = - 10 A IOH = - 1.6 mA IOH = - 3.2 mA REXT = (3) (3) Conditions 1-90 * Advance information: ISD2532/40/48/64 devices. Product Data Sheets ISD2500 Series DC PARAMETERS (PACKAGED PARTS) - CONTINUED Symbol RANA IN APRE1 APRE2 AAUX AARP RAGC NOTES: Parameters ANA IN Input Resistance Preamp Gain 1 Preamp Gain 2 AUX IN/SP+ Gain ANA IN to SP+/- Gain AGC Output Resistance Min(2) 2.3 21 Typ (1) 3 24 -15 0.98 Max(2) 5 26 5 1.0 26 9.5 Units K dB dB V/V dB K Conditions AGC = 0.0 V AGC = 2.5 V 21 2.5 23 5 1. Typical values @ TA = 25 C and 5.0 V. 2. All Min/Max limits are guaranteed by ISD via electrical testing or characterization. Not all specifications are 100% tested. 3. VCCA and VCCD connected together. 4. XCLK pin only. 1 Conditions (7) (7) (7) (7) (7) (7) (7) (7) AC PARAMETERS (PACKAGED PARTS) Symbol FS Sampling Frequency Characteristic -- ISD2532* -- ISD2540* -- ISD2548* -- ISD2564* -- ISD2560 -- ISD2575 -- ISD2590 -- ISD25120 -- ISD2532* -- ISD2540* -- ISD2548* -- ISD2564* -- ISD2560 -- ISD2575 -- ISD2590 -- ISD25120 Min(2) Typ (1) Max(2) Units 8.0 6.4 5.3 4.0 8.0 6.4 5.3 4.0 3.4 2.7 2.3 1.7 3.4 2.7 2.3 1.7 KHz KHz KHz KHz KHz KHz KHz KHz KHz KHz KHz KHz KHz KHz KHz KHz FCF Filter Pass Band 3 dB Roll-Off Point (3) (8) 3 dB Roll-Off Point (3) (8) 3 dB Roll-Off Point (3) (8) 3 dB Roll-Off Point (3) (8) 3 dB Roll-Off Point (3) (8) 3 dB Roll-Off Point (3) (8) 3 dB Roll-Off Point (3) (8) 3 dB Roll-Off Point (3) (8) * Advance information: ISD2532/40/48/64 devices. 1-91 ISD2500 Series Product Data Sheets AC PARAMETERS (PACKAGED PARTS) - CONTINUED Symbol TREC Record Duration Characteristic -- ISD2532* -- ISD2540* -- ISD2548* -- ISD2564* -- ISD2560 -- ISD2560 -- ISD2575 -- ISD2575 -- ISD2590 -- ISD25120 -- ISD2532* -- ISD2540* -- ISD2548* -- ISD2564* -- ISD2560 -- ISD2560 -- ISD2575 -- ISD2575 -- ISD2590 -- ISD25120 Min(2) Typ (1) Max(2) Units Conditions 58.1 56.5 72.6 70.7 87.1 116.1 32.0 40.0 48.0 64.0 60.0 60.0 75.0 75.0 90.0 120.0 32.0 40.0 48.0 64.0 60.0 60.0 75.0 75.0 90.0 120.0 100 300 0 62.0 63.8 77.5 79.7 93.0 123.9 sec sec sec sec sec sec sec sec sec sec sec sec sec sec sec sec sec sec sec sec nsec nsec nsec Commercial Operation Industrial Operation Commercial Operation Industrial Operation Commercial Operation Commercial Operation (7) (7) (7) (7) TPLAY Playback Duration -1 TCE TSET THOLD TPUD CE Pulse Width 58.1 56.5 72.6 70.7 87.1 116.1 62.0 63.8 77.5 79.7 93.0 123.9 Commercial Operation(7) Industrial Operation(7) Commercial Operation(7) Industrial Operation(7) Commercial Operation(7) Commercial Operation(7) Control/Address Setup Time Control/Address Hold Time Power-Up Delay -- ISD2532* -- ISD2540* -- ISD2548* -- ISD2564* -- ISD2560 -- ISD2560 -- ISD2575 -- ISD2575 -- ISD2590 -- ISD25120 -- ISD2532* -- ISD2540* -- ISD2548* -- ISD2564* -- ISD2560 -- ISD2575 -- ISD2590 -- ISD25120 24.1 23.5 30.2 29.3 36.2 48.2 25.0 31.3 37.5 50.0 25.0 25.0 31.3 31.3 37.5 50.0 25 31.25 37.5 50.0 25 31.25 37.5 50.0 27.8 28.5 34.3 35.2 40.8 53.6 msec msec msec msec msec msec msec msec msec msec msec msec msec msec msec msec msec msec Commercial Operation Industrial Operation Commercial Operation Industrial Operation Commercial Operation Commercial Operation TPDR PD Pulse Width Record 1-92 * Advance information: ISD2532/40/48/64 devices. Product Data Sheets ISD2500 Series AC PARAMETERS (PACKAGED PARTS) - CONTINUED Symbol TPDP PD Pulse Width Play Characteristic -- ISD2532* -- ISD2540* -- ISD2548* -- ISD2564* -- ISD2560 -- ISD2575 -- ISD2590 -- ISD25120 Min(2) Typ (1) Max(2) Units Conditions 12.5 15.625 18.75 25.0 12.5 15.625 18.75 25.0 100 0 msec msec msec msec msec msec msec msec nsec nsec (6) TPDS TPDH TEOM PD Pulse Width Static Power Down Hold EOM Pulse Width -- ISD2532* -- ISD2540* -- ISD2548* -- ISD2564* -- ISD2560 -- ISD2575 -- ISD2590 -- ISD25120 12.5 15.625 18.75 25.0 12.5 15.625 18.75 25.0 6.5 1 12.2 2 50 2.5 20 50 1.25 msec msec msec msec msec msec msec msec sec % mW V p-p mV mV V @ 1 KHz REXT = 16 (4) REXT = 600 Peak-to-Peak (5) Peak-to-Peak Peak-to-Peak; REXT = 16 1 TOVF THD POUT VOUT VIN1 VIN2 VIN3 Overflow Pulse Width Total Harmonic Distortion Speaker Output Power Voltage Across Speaker Pins MIC Input Voltage ANA IN Input Voltage Aux Input Voltage NOTES: 1. Typical values @ TA = 25 C and 5.0 V. 2. All Min/Max limits are guaranteed by ISD via electrical testing or characterization. Not all specifications are 100% tested. 3. Low-frequency cutoff depends upon the value of external capacitors (see Pin Descriptions). 4. From AUX IN; if ANA IN is driven at 50 mV p-p, the POUT=12.2 mW, typical. 5. With 5.1 K series resistor at ANA IN. 6. TPDS is required during a static condition, typically overflow. 7. Sampling Frequency and Playback Duration can vary as much as 2.25% over the commercial temperature range and voltage range and 5% over the industrial temperature and voltage range. For greater stability, an external clock can be utilized (see Pin Descriptions). 8. Filter specification applies to the antialiasing filter and the smoothing filter. * Advance information: ISD2532/40/48/64 devices. 1-93 ISD2500 Series Product Data Sheets TYPICAL PARAMETER VARIATION WITH VOLTAGE AND TEMPERATURE (PACKAGED PARTS) RECORD MODE OPERATING CURRENT (ICC) 25 Operating Current (mA) 1.2 1.0 0.8 0.6 0.4 0.2 0 25 70 85 -40 STANDBY CURRENT (ISB) 15 10 5 -1 0 -40 Temperature (C) Standby Current (A) 20 25 70 85 Temperature (C) TOTAL HARMONIC DISTORTION 0.7 0.6 Percent Distortion (%) 0.5 0.4 0.3 0.2 0.1 0 -40 25 70 85 Percent Change (%) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -40 OSCILLATOR STABILITY 25 70 85 Temperature (C) Temperature (C) 5.5 Volts 4.5 Volts 1-94 * Advance information: ISD2532/40/48/64 devices. Product Data Sheets ISD2500 Series ABSOLUTE MAXIMUM RATINGS (DIE) Condition Junction temperature Storage temperature range Voltage applied to any pad 150 C -65 C to +150 C (VSS - 0.3 V) to (VCC + 0.3 V) (VSS - 1.0 V) to (VCC + 1.0 V) - 0.3 V to + 7.0 V Value OPERATING CONDITIONS (DIE) Condition Commercial operating temperature range Supply voltage (VCC)(1) Ground voltage (VSS)(2) NOTES: 1. VCC = VCCA = VCCD. 2. VSS = VSSA = VSSD. Value 0 C to +50 C +4.5 V to +6.5 V 0V Voltage applied to any pad (Input current limited to + 20 mA) VCC - VSS NOTE: Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability. Functional operation is not implied at these conditions. 1 Typ (1) Max(2) 0.8 Units V V 0.4 V V V VCC-0.8 25 1 30 10 +1 130 V mA A A A 9 11 3 15 20 5 K K K Force VCC (4) Speaker Load MIC and MIC REF Pads IOL = 4.0 mA IOH = - 10 A IOH = - 1.6 mA IOH = - 3.2 mA REXT = (3) (2) DC PARAMETERS (DIE) Symbol VIL VIH VOL VOH VOH1 VOH2 ICC ISB IIL IILPD REXT RMIC RAUX RANA IN Parameters Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage OVF Output High Voltage EOM Output High Voltage VCC Current (Operating) VCC Current (Standby) Input Leakage Current Input Current HIGH w/Pull Down Output Load Impedance Preamp In Input Resistance AUX INput Resistance ANA IN Input Resistance 16 4 5 2.3 VCC-0.4 2.4 VCC-1.0 2.0 Min(2) Conditions * Advance information: ISD2532/40/48/64 devices. 1-95 ISD2500 Series Product Data Sheets DC PARAMETERS (DIE) - CONTINUED Symbol APRE1 APRE2 AAUX AARP RAGC NOTES: Parameters Preamp Gain 1 Preamp Gain 2 AUX IN/SP+ Gain ANA IN to SP+/- Gain AGC Output Resistance Min(2) 21 Typ (1) 24 - 15 0.98 Max(2) 26 5 1.0 26 9.5 Units dB dB V/V dB K Conditions AGC = 0.0 V AGC = 2.5 V 21 2.5 23 5 1. Typical values @ TA = 25 C and 5.0 V. 2. All Min/Max limits are guaranteed by ISD via electrical testing or characterization. Not all specifications are 100% tested. 3. VCCA and VCCD connected together. 4. XCLK pad only. -1 AC PARAMETERS (DIE) Symbol FS Sampling Frequency Characteristic -- ISD2532* -- ISD2540* -- ISD2548* -- ISD2564* -- ISD2560 -- ISD2575 -- ISD2590 -- ISD25120 -- ISD2532* -- ISD2540* -- ISD2548* -- ISD2564* -- ISD2560 -- ISD2575 -- ISD2590 -- ISD25120 TREC Record Duration -- ISD2532* -- ISD2540* -- ISD2548* -- ISD2564* -- ISD2560 -- ISD2575 -- ISD2590 -- ISD25120 Min(2) Typ (1) Max(2) Units Conditions (7) (7) (7) (7) (7) (7) (7) (7) 8.0 6.4 5.3 4.0 8.0 6.4 5.3 4.0 3.4 2.7 2.3 1.7 3.4 2.7 2.3 1.7 KHz KHz KHz KHz KHz KHz KHz KHz KHz KHz KHz KHz KHz KHz KHz KHz FCF Filter Pass Band 3 dB Roll-Off Point (3) (8) 3 dB Roll-Off Point (3) (8) 3 dB Roll-Off Point (3) (8) 3 dB Roll-Off Point (3) (8) 3 dB Roll-Off Point (3) (8) 3 dB Roll-Off Point (3) (8) 3 dB Roll-Off Point (3) (8) 3 dB Roll-Off Point (3) (8) 58.1 72.6 87.1 116.1 32.0 40.0 48.0 64.0 60.0 75.0 90.0 120.0 62.0 77.5 93.0 123.9 sec sec sec sec sec sec sec sec Commercial Operation Commercial Operation Commercial Operation Commercial Operation 1-96 * Advance information: ISD2532/40/48/64 devices. Product Data Sheets ISD2500 Series AC PARAMETERS (DIE) - CONTINUED Symbol TPLAY Playback Duration Characteristic -- ISD2532* -- ISD2540* -- ISD2548* -- ISD2564* -- ISD2560 -- ISD2575 -- ISD2590 -- ISD25120 Min(2) Typ (1) Max(2) Units Conditions (7) (7) (7) (7) 58.1 72.6 87.1 116.1 32.0 40.0 48.0 64.0 60.0 75.0 90.0 120.0 100 300 0 62.0 77.5 93.0 123.9 sec sec sec sec sec sec sec sec nsec nsec nsec Commercial Operation(7) Commercial Operation(7) Commercial Operation(7) Commercial Operation(7) TCE TSET THOLD TPUD CE Pulse Width Control/Address Setup Time Control/Address Hold Time Power-Up Delay -- ISD2532* -- ISD2540* -- ISD2548* -- ISD2564* -- ISD2560 -- ISD2575 -- ISD2590 -- ISD25120 -- ISD2532* -- ISD2540* -- ISD2548* -- ISD2564* -- ISD2560 -- ISD2575 -- ISD2590 -- ISD25120 -- ISD2532* -- ISD2540* -- ISD2548* -- ISD2564* -- ISD2560 -- ISD2575 -- ISD2590 -- ISD25120 24.1 30.2 36.2 48.2 25.0 31.3 37.5 50.0 25.0 31.3 37.5 50.0 25 31.25 37.5 50.0 25 31.25 37.5 50.0 12.5 15.625 18.75 25.0 12.5 15.625 18.75 25.0 100 0 27.8 34.3 40.8 53.6 msec msec msec msec msec msec msec msec msec msec msec msec msec msec msec msec msec msec msec msec msec msec msec msec nsec nsec 1 Commercial Operation Commercial Operation Commercial Operation Commercial Operation TPDR PD Pulse Width Record TPDP PD Pulse Width Play TPDS TPDH PD Pulse Width Static Power Down Hold (6) * Advance information: ISD2532/40/48/64 devices. 1-97 ISD2500 Series Product Data Sheets AC PARAMETERS (DIE) - CONTINUED Symbol TEOM Characteristic EOM Pulse Width -- ISD2532* -- ISD2540* -- ISD2548* -- ISD2564* -- ISD2560 -- ISD2575 -- ISD2590 -- ISD25120 Min(2) Typ (1) Max(2) Units Conditions 12.5 15.625 18.75 25.0 12.5 15.625 18.75 25.0 6.5 1 12.2 3 50 2.5 20 50 1.25 msec msec msec msec msec msec msec msec sec % mW V p-p mV mV V @ 1 KHz REXT = 16 (4) REXT = 600 Peak-to-Peak (5) Peak-to-Peak Peak-to-Peak; REXT = 16 TOVF THD POUT VOUT Overflow Pulse Width Total Harmonic Distortion Speaker Output Power Voltage Across Speaker Pins MIC Input Voltage ANA IN Input Voltage Aux Input Voltage -1 VIN1 VIN2 VIN3 NOTES: 1. Typical values @ TA = 25 C and 5.0 V. 2. All Min/Max limits are guaranteed by ISD via electrical testing or characterization. Not all specifications are 100% tested. 3. Low-frequency cutoff depends upon the value of external capacitors (see Pin Descriptions). 4. From AUX IN; if ANA IN is driven at 50 mV p-p, the POUT=12.2 mW, typical. 5. With 5.1 K series resistor at ANA IN. 6. TPDS is required during a static condition, typically overflow. 7. Sampling Frequency and Playback Duration can vary as much as 2.25% over the commercial temperature range and voltage range. For greater stability, an external clock can be utilized (see Pin Descriptions). 8. Filter specification applies to the antialiasing filter and the smoothing filter. 1-98 * Advance information: ISD2532/40/48/64 devices. Product Data Sheets ISD2500 Series TYPICAL PARAMETER VARIATION WITH VOLTAGE AND TEMPERATURE (DIE) RECORD MODE OPERATING CURRENT (ICC) 30 Operating Current (mA) 25 20 15 10 5 0 0 25 Temperature (C) 50 1.0 STANDBY CURRENT (ISB) Standby Current (A) 0.8 0.6 0.4 0.2 1 0 0 25 Temperature (C) 50 TOTAL HARMONIC DISTORTION 0.7 0.6 Percent Distortion (%) 0.5 0.4 0.3 0.2 0.1 0 0 25 Temperature (C) 50 Percent Change (%) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 OSCILLATOR STABILITY 25 Temperature (C) 50 6.5 Volts 5.5 Volts 4.5 Volts * Advance information: ISD2532/40/48/64 devices. 1-99 ISD2500 Series Product Data Sheets ISD2500 APPLICATION EXAMPLE - DESIGN SCHEMATIC ISD2500 (PDIP/SOIC) 1 2 3 4 V CC V CC VSS R4 100 K 5 6 7 8 CHIP ENABLE 9 10 A0 A1 A2 A3 A4 A5 A6 A7 (NC*) A8 (A7*) A9 (A8*) CE PD P/R EOM OVF XCLK VCCD 28 VCCA 16 VSSD VSSA SP+ SP- AUX IN ANA IN ANA OUT MIC REF** MIC AGC 12 13 C6 0.1 F C8 C7 0.1 F 22 F 14 15 11 20 16 SPEAKER C3 0.1 F R 6 5.1 K POWER DOWN 23 24 27 25 21 18 17 PLAYBACK/RECORD 22 26 -1 19 V CC C1 0.1 F R3 10 K ELECTRET MICROPHONE C5 0.1 F R1 1 K R2 470 K C2 4.7 F C4 220 F R5 10 K NOTES: * Pin identifications for the ISD2532/40/48/64 devices which differ from those of the ISD2560/75/90/120 devices are indicated. ** If desired, pin 18 (PDIP package) may be left unconnected (microphone preamplifier noise will be higher). In this case, pin 18 must not be tied to any other signal or voltage. Additional design example schematics are provided in the Application Notes and Design Manual in this book. APPLICATION EXAMPLE - BASIC DEVICE CONTROL Control Step 1 2 3A 3B 4A 4B Function Power up chip and select Record/Playback mode Set message address for Record/Playback Begin Playback Begin Record End Playback End Record Action 1. PD = LOW, 2. P/R = As desired Set addresses A0-A9 P/R = HIGH, CE = Pulsed LOW P/R = LOW, CE = LOW Automatic PD or CE = HIGH 1-100 * Advance information: ISD2532/40/48/64 devices. Product Data Sheets ISD2500 Series APPLICATION EXAMPLE - PASSIVE COMPONENT FUNCTIONS Part R1 R2 R3, R5 R4 R6 C1, C5 Function Microphone power supply decoupling Release time constant Microphone biasing resistors Series limiting resistor Series limiting resistor Microphone DC-blocking capacitor Low-frequency cutoff Attack/Release time constant Low-frequency cutoff capacitor Microphone power supply decoupling Power supply capacitors Comments Reduces power supply noise Sets release time for AGC Provides biasing for microphone operation Reduces level to prevent distortion at higher supply voltages. Reduces level to high supply voltages Decouples microphone bias from chip. Provides singlepole low-frequency cutoff and common mode noise rejection. Sets attack/release time for AGC Provides additional pole for low-frequency cutoff Reduces power supply noise Filter and bypass of power supply C2 C3 C4 C6, C7, C8 1 EXPLANATION In this simplified block diagram of a microcontroller application, the Push-Button mode and message cueing are used. The microcontroller is a 16-pin version with enough port pins for buttons, an LED, and the ISD2500 Series device. The software can be written to use three buttons: one each for play and record, and one for message selection. Because the microcontroller is interpreting the buttons and commanding the ISD2500 device, software can be written for any functions desired in a particular application. NOTE ISD does not recomend connecting address lines directly to a microprocessor bus. Address lines should be externally latched. * Advance information: ISD2532/40/48/64 devices. 1-101 ISD2500 Series Product Data Sheets ISD2500 APPLICATION EXAMPLE - MICROCONTROLLER/ISD2500 INTERFACE V CC D1 RUN S1 RECORD S2 PLAY S3 MSG# MC68HC705K1A OSC1 OSC2 RESET IRQ U1 VDD V SS PB0 PB1 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 R1 TBD ISD2500 (PDIP/SOIC) 1 2 3 4 5 6 7 8 9 10 -1 A0 A1 A2 A3 A4 U2 A5 A6 A7 (NC*) A8 (A7*) A9 (A8*) CE PD P/R EOM OVF XCLK 28 CCD CCA 12 SSD SSA 14 15 11 20 13 16 23 24 27 25 22 26 21 18 17 19 NOTES: * Pin identifications for the ISD2532/40/48/64 devices which differ from those of the ISD2560/75/90/120 devices are indicated. 1-102 * Advance information: ISD2532/40/48/64 devices. Product Data Sheets ISD2500 Series ISD2500 APPLICATION EXAMPLE - PUSH-BUTTON ISD2500 (PDIP/SOIC) 1 V CC V CC VSS 2 3 4 V CC S1 R6 100 K R7 100 K V CC 5 6 7 8 9 10 START/PAUSE S2 STOP/RESET A0 A1 A2 A3 A4 A5 A6 A7 (NC*) A8 (A7*) A9 (A8*) CE PD P/R EOM OVF XCLK VCCD 28 VCCA 16 VSSD VSSA SP+ SP- AUX IN ANA IN ANA OUT MIC REF MIC AGC 12 13 C4 0.1 F C1 0.1 F C5 22 F 14 15 11 20 LS1 16 SPEAKER C3 0.1 F R 4 5.1 K 23 24 27 25 21 18 17 PLAYBACK/RECORD 22 26 19 V CC C1 0.1 F R3 10 K C5 0.1 F 1 R2 470 K C2 4.7 F C4 220 F ELECTRET MICROPHONE R5 10 K NOTES: * Pin identifications for the ISD2532/40/48/64 devices which differ from those of the ISD2560/75/90/120 devices are indicated. ** For more details, please refer to the ISD Application Notes and Design Manual. APPLICATION EXAMPLE - PUSH-BUTTON CONTROL Control Step 1 2A 2B 3 4A 4B Function Select Record/Playback mode Begin Playback Begin Record Pause Record or Playback End Payback End Record Action P/R = As desired P/R = HIGH CE = Pulsed LOW P/R = LOW CE = Pulsed LOW CE = Pulsed LOW Automatic at EOM marker or PD = Pulsed HIGH PD = Pulsed HIGH * Advance information: ISD2532/40/48/64 devices. 1-103 ISD2500 Series Product Data Sheets APPLICATION EXAMPLE - PASSIVE COMPONENT FUNCTIONS Part R2 R4 R6, R7 C1, C4, C5 C2 C3 Function Release time constant Series limiting resistor Pull-up and pull-down resistors Power supply capacitors Attack/Release time constant Low-frequency cutoff capacitor Comments Sets release time for AGC Reduces level to prevent distortion at higher supply voltages Defines static state of inputs Filters and bypass of power supply Sets attack/release time for AGC Provides additional pole for lowfrequency cutoff -1 PUSH-BUTTON PARAMETERS Symbol TCE TSET TPUD Characteristic CE Pulse Width [Start/Pause] Control/Address Setup Time Power-Up Delay -- ISD2532* -- ISD2540* -- ISD2548* -- ISD2564* -- ISD2560 -- ISD2575 -- ISD2590 -- ISD25120 Min Typ (1) 300 300 25 31.25 37.25 50.0 25 31.25 37.25 50.0 300 25 50 -- ISD2532* -- ISD2540* -- ISD2548* -- ISD2564* -- ISD2560 -- ISD2575 -- ISD2590 -- ISD25120 70 85 105 135 70 85 105 135 400 400 105 135 160 215 105 135 160 215 Max Units nsec nsec msec msec msec msec msec msec msec msec nsec nsec nsec msec msec msec msec msec msec msec msec Conditions TPD TRUN TPAUSE TDB PD Pulse Width [Stop/Reset] CE to EOM HIGH CE to EOM LOW CE HIGH Debounce 1-104 * Advance information: ISD2532/40/48/64 devices. Product Data Sheets ISD2500 Series TIMING DIAGRAMS Push-Button Mode Record "Start" TCE CE (Start/Pause) P/R PD (Stop/Reset) A0-A9 MIC ANA IN OVF EOM (Run) TPUD Notes: (1) (2) (3) (4, 5) "Pause" TCE TSET "Start" TCE "Stop" TSET TSET TSET TSET TPD TSET TRUN TDB TPAUSE TDB TPUD (6, 7) TDB (8) 1 Push-Button Mode Playback "Start" TCE CE (Start/Pause) P/R PD (Stop/Reset) A0-A9 SP+/- OVF EOM (Run) TPUD Notes: (1) (2) (3) "Pause" TCE TSET "Start" TCE "Stop" TSET TSET TSET TSET TPD TSET TRUN TDB (4, 5) TPAUSE TDB TPUD (6, 7) TDB (8) NOTES: 1. 2. 3. 4. 5. 6. 7. 8. A9, A8, and A6 = 1 for push-button operation. The first CE LOW pulse performs a Start function. The part will begin to play or record after a power-up delay TPUD. The part must have CE HIGH for a debounce period TDB before it will recognize another falling edge of CE and pause. The second CE LOW pulse, and every even pulse thereafter, performs a Pause function. Again, the part must have CE HIGH for a debounce period TDB before it will recognize another falling edge of CE, which would restart an operation. In addition, the part will not do an internal power down until CE is HIGH for the TDB time. The third CE LOW pulse, and every odd pulse thereafter, performs a Resume function. At any time, a HIGH level on PD will stop the current function, reset the address counter, and power down the device. * Advance information: ISD2532/40/48/64 devices. 1-105 ISD2500 Series Product Data Sheets ORDERING INFORMATION Product Number Descriptor Key ISD25 _ _ _ _ 2 = 2nd Generation 5 = 5 Volts Duration: 32 = 32 Seconds* 40 = 40 Seconds* 48 = 48 Seconds* 64 = 64 Seconds* 60 = 60 Seconds 75 = 75 Seconds 90 = 90 Seconds 120 = 120 Seconds Special Temperature Field: Blank = Commercial Packaged (0C to +70C) or Commercial Die (0C to +50C) I = Industrial (-40C to +85C) Package Type: E = 28-Lead 8x13.4-mm Thin Small Outline Package (TSOP) P = 28-Lead 0.600-Inch Plastic Dual In-Line Package (PDIP) S = 28-Lead 0.300-Inch Small Outline Integrated Circuit (SOIC) T = 32-Lead 8x20-mm Thin Small Outline Package (TSOP) X = Die -1 When ordering ISD2500 Series devices, please refer to the following valid part numbers. Part Number ISD2560E ISD2560EI ISD2560P ISD2560PI ISD2560S ISD2560SI ISD2560T ISD2560TI ISD2560X Part Number ISD2575E ISD2575EI ISD2575P ISD2575PI ISD2575S ISD2575SI ISD2575T ISD2575TI ISD2575X Part Number ISD2590E ISD2590P ISD2590S ISD2590T ISD2590X Part Number ISD25120P ISD25120X For the latest product information, access ISD's worldwide website at http://www.isd.com. 1-106 * Advance information: ISD2532/40/48/64 devices. |
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